Tombstoning on small SMT chip packages is a common defect in electronic manufacturing. Multiple contributing factors can cause this phenomenon including varying thermal mass between opposing pads. The reflow profile can have a direct impact on tombstone occurrences. Two common industry profile techniques are used to compare the effects on tombstones with end of line defect data. Visual verification is done by duplicating test profiles on a rework station. The results show a clear benefit of one profile technique over another to reduce tombstoning.